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Re: {SPAM?} Re: [linrad] RE: Detecting phase modulation with undersampling

Quoting "Dr. David Kirkby" <drkirkby@xxxxxxxxxxxxxxxxx>:
> Krzysztof Kamieniecki wrote:
> > This seems like a fully digital RF lock-in amplifier, 
> Yes, basically it is.
> > of which I have not seen an off-the-self model. 
> They do exist - I bought one at the around 1995 when I started my PhD. 
> However, the only high frequency versions I am aware of use a mixer to 
> down-convert, then do the processing at lower frequencies.

Yes, that was what I meant, I have never seen a direct conversion Lockin for RF
frequencies. We at one point we used lockins in our products at work, but when
they were end-of-lifed we switched to a custom board, with a 10MS/s A/D and
some digital COTS down-converter ASICs.

> That implements an IQ demodulator on the DSP - an approach I think might 
> be the right one.
> >
> > Disclaimer: I'm a Software Developer and amateur EE. 
> Don't worry. I develop software too - I tend to do a bit of everything - 
> RF, optics, software, now starting on DSP.
> > How about this?
> >
> > R = real reference signal sampled at 65MHz
> > S = real signal of interest sampled at 65MHz
> >
> > Down-convert R and S separately to two low bandwidth/sample rate 
> > complex signals, possibly with a CIC[1] filter but there is probably a 
> > better method, since CIC is well suited for FPGAs and ASICs. 
> I hope to do all the processing on the board I have. I certainly want to 
> avoid FPGS's - I believe they are quite sepecialled, and need someone 
> who is really an expert on them. The company selling the board I have 
> has some FPGA based models, but warned me that you really need an 'FPGA 
> engineer' to use them - they are far from easy to use.

Take a look at this paper, section 3.1 is of particular interest
It contains information about a software radio down-converter, GNURadio may use
this algorithm but I am not sure. It seems to cut down significantly on
processing power needed to do down-conversion.

If you can get the undersampling just right, you could get away with decimation
instead of the more complex down-conversion.

> > At this point you could divide S by R (since the sample rate will be 
> > relatively low on the order of 5KS/s the c6701 may be able to handle it). 
> I hope the C6701 can do that!! It is clocked at 150 MHz I think. I'm not 
> sure a division is the way to go though. However, I am not convinced a 
> division is the way to go. What makes you suggest that??

The marketing blurb says 900MFLOPS @ 150MHz, after some more investigation it
looks like the c6701 has 2 sets of 1 Multiplier & 2 non-symmetric ALUs . I
don't know what the gotchas are so the real processing power of the c6701 may
not be enough power for what I proposed. 

As for the division, my thought was that you could calculate the phase shift and
gain vs the reference signal by dividing the complex signal of interest by the
complex reference signal. The c6701 has some hardware support for division, in
the form of a approximate reciprocal instruction, so it may be able to do this
in real time for low sample rates.

Being able to use the method I proposed comes down to what is the maximum sample
rate that the c6701 board can acquire and down-convert. I am not certain about
undersampling noise performance.