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[linrad] Re: Linrad via Ethernet

Leif wrote:

Hmmm, maybe one could use a pair of AD6620s. The problem is that it
does not have a resampler so one has to use minimum decimation on
the filters.


<snip discussion of AD6620 filtering>
I hadn't looked that close yet. Maybe the AD6620 data sheet deserves more than 'a brief look'... 


Maybe it would be better to use some general purpose gate array
for the second filter. I do not like the idea of allowing the PC
to receive oversampled signals because any spare processing power
it might have can be put to bettert use:-)


I respectfully disagree.
For ham/hobbyist purposes, *nothing* beats the price/performance of commodity PC hardware. I just had a look on eBay; I can get a PIII/933 with 256MB RAM and no disk for EUR80 + shipping. And that's from a store; similar hardware can usually be had for very little from people who've upgraded their system twice since.
IMHO, actual hand-soldered hardware should be limited to the absolute minimum to get raw data to a PC. The more complex the design, the less likely that it will work first time around (and 4-layer protos are getting cheap but not *that* cheap). FPGAs are nice, but how many people have the skills to program them well? A much larger target audience will be able to code filters in C than in VHDL, and there are plenty of free signal processing libraries out there.
Is one cheap PC not enough for filtering *and* Linrad ? Add another PC, and dedicate one to filtering/decimating. Need/want to do contests 'in the field' ? Search on eBay for 'laptop broken screen'. That's how I ended up with an Athlon/1.2GHz for US$75 (plus shipping, but that's a whole 'nother rant). 


Some more bandwidth is highly desireable (to fight static rain well.)
Two channels (provision for syncing several units) is required for
use with Linrad on a X-yagi array for EME. More channels would
be extremely valuable on HF bands. (On HF less bandwidth is needed
so the PC will have no problems)
Absolutely agreed. I'm building mine as a testbed for diversity/MIMO experiments, so the thing will definitely have the ability to slave additional units. I like to have my synth/sample clocks synchronized. 


The SDR-14 with an ethernet interface, a digital filter in a gate
array


Like http://comsec.com/wiki?UniversalSoftwareRadioPeripheral ; you mean ?


      and a better sampling clock would be one solution:-)
This is one area where I am very interested in your suggestions; I was quite impressed by the depth of your discussions on oscillators on the Linrad pages.
What would 'a better sampling clock' look like in your opinion ? My current line of thinking is to have one reference OCXO/TCXO (possibly disciplined *very slowly* by GPS), with other frequencies generated by locking low distortion VCXOs/VCCROs to this reference. Add transformer-fed low jitter LVDS->CMOS converters (or fast low jitter comparators, like the Linear LT1720) to generate the ADC sample clock if needed (ie: if the jitter performance of the ADC clock input is worse for AC-coupled sine waves than for CMOS, need to investigate this).
Random thought: instead of locked VCXOs, maybe have a separate digital channel record the frequency/phase differences wrt the reference clock and have software correct for these. Hmmm... 

Thoughts ? Suggestions ? Flames ? ;-)

JDB.
--
LART. 250 MIPS under one Watt. Free hardware design files.
http://www.lart.tudelft.nl/

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